1. Field of the Invention
The present invention relates to a bidirectional shift register which can switch the order of output of pulses and an image display device which uses the bidirectional shift register to drive the respective scanning lines.
2. Description of the Related Art
Higher resolution of a liquid crystal display device is materialized by improving the arrangement density of pixels in a display portion thereof. As the arrangement density is improved, the arrangement pitch of various kinds of signal lines for supplying signals to pixel circuits becomes finer. Gate lines provided correspondingly to scanning lines of pixels are connected to gate line driving circuits on sides of a display region. A gate line driving circuit includes a shift register for outputting to the respective scanning lines in sequence a voltage which enables writing data to a pixel circuit. As the resolution becomes higher, unit register circuits included in the respective stages of the shift register are also required to be reduced in size.
Ordinarily, a voltage is applied to gate lines in a top to bottom order of an image correspondingly to an order of input of image data in a vertical scanning direction. If the shift register may be driven bidirectionally, input image data may be written to pixel circuits in a bottom to top order when the scan line goes from the bottom to the top. This enables change in the direction of a displayed image with a mechanism that is simpler than that in a structure in which a frame memory for buffering image data or the like is provided and the order of the image data is changed thereby.
A shift register used in a gate line driving circuit or the like includes cascaded unit register circuits in a plurality of stages. Basically, operation in which the respective unit register circuits in the respective stages output a pulse once in an order from one end to the other end of the row of the unit register circuits is performed, the operation being linked with vertical scanning or the like.
FIG. 14 is a circuit diagram illustrating a basic structure of a unit register circuit (see Japanese Patent Application Laid-open Nos. 2004-157508 and 2009-272037). In a unit register circuit in an n-th stage, an output transistor M1 is connected between an output terminal (GOUT[n]) and a clock signal source CK, while a transistor M2 is connected between the terminal (GOUT[n]) and a power supply VOFF. FIG. 15 is a signal waveform chart illustrating operation of the unit register circuit illustrated in FIG. 14. When an output pulse GOUT[n−1] in the previous stage is input to the unit register circuit, a node N3 (one end of a capacitor C) connected to a gate of M1 is connected to a power supply VON, and a potential of the node N3 is pulled up to a High (H) level which is a potential at which the transistor is turned on. When the node N3 is at the H level, a node N4 is connected to the power supply VOFF to be set to a Low (L) level which is a potential at which the transistor is turned off, thereby turning off the transistor M2. In this way, the unit register circuit is in a set state. In this state, when a clock signal CKV (CK) transitions from the L level to the H level, the potential of the node N3 is further pulled up via the capacitor C connected between the gate and a source of the output transistor M1, and the clock signal CKV at the H level is output from the terminal GOUT[n].
On the other hand, in the case of transition of the clock signal CKV from the H level to the L level, the potential of the node N3 is pulled down and a voltage at the output terminal GOUT[n] is also pulled down. Here, linked with a rising edge of a clock signal CKB to an (n+1)th stage, a pulse is generated in an output signal GOUT[n+1] in the subsequent stage, which is input to the unit register circuit in the n-th stage. The pulse of GOUT[n+1] pulls down the potential of the node N3. This pulls up a potential of the node N4, the transistor M2 is turned on, and the output terminal is connected to the power supply VOFF. By the operation, a pulse of the output signal GOUT[n] is output.